Field of the Invention
The present invention relates to a field effect transistor (FET: Field Effect Transistor) formed over an SOI (Silicon On Insulator) substrate, and particularly to a field effect transistor having an elevated source/drain structure, which is manufactured by selectively epitaxial growth on a source/drain region alone after the formation of the source/drain region, and a method of manufacturing the same.
Description of the Related Art
The formation of a field effect transistor over an SOI substrate as an alternative to a conventional bulk semiconductor substrate has been performed in recent years. The SOI-FET has the merit that it is structurally small in parasitic capacity, latchup-free, low in soft error rate, and relatively easy in element isolation, for example. Therefore, great attention has recently been focused on the possibility of application to a high-speed and low power consumption LSI. A fully depletion type SOI-FET has an advantage in that since a depletion layer formed below a gate electrode reaches an buried oxide film below an SOI layer, the depletion layer becomes small in capacitance and a subthreshold coefficient is reduced to a substantially ideal value.
The implementation of a complete depletion type SOI-FET having a micro gate length needs to increase the concentration of an impurity in a channel region, restrain the extension of a depletion layer from a source/drain region, and control a short channel effect by an increase in charge share coefficient. On the other hand, since the expansion of the depletion layer below a gate electrode becomes narrow as the concentration of the impurity in the channel increases, it is necessary to thin the thickness of an SOI layer for the purpose of performing a fully depletion type operation (allowing the depletion layer to reach an buried oxide film). When the gate length is less than or equal to 0.2 xcexcm, the thickness of the SOI layer must be thinned to a thickness of from 20 nm to 50 nm. Therefore, a source/drain resistance increases and hence a transistor characteristic is degraded.
As a method of reducing the source/drain resistance, for example, a salicide process for selectively forming a silicide layer comprised of titanium (Ti) and/or cobalt (Co) in a source/drain region has been used. However, when the thickness of the SOI layer becomes thinner than 50 nm, it is known that it becomes difficult to form the silicide layer. When the silicide layer is formed so as to reach the buried oxide film, an aggregation is apt to occur, thus causing the possibility that an increase in resistance and fractures in channel and source/drain regions will occur. A problem arises in that when silicidation is made with the SOI layer left behind, the resistance of the silicide layer is not sufficiently lowered or no silicide layer is formed over a thin-line portion. From the viewpoint of such a background, a method of selectively epitaxially-growing a silicon layer over a source/drain region preceding the execution of the salicide process, thickening the silicon layer in the source/drain region and thereafter forming a silicide layer is now adopted.
However, the process of selectively epitaxially-growing the silicon layer thereon needed to perform heat treatment at a high temperature of at least 930xc2x0 C. or higher in a hydrogen atmosphere for the purpose of removing a native oxide film over the surface of an SOI layer. A problem has been confirmed in that when a temperature profile in such a selective epitaxial-growth process is used, atoms of silicon begin to aggregate from an end of an SOI layer pattern during high-temperature heat treatment. As a result, there is a possibility that the shape of the source/drain region in the SOI layer will break down, thus making it impossible to implement the SOI-FET.
With the foregoing in view, it is therefore an object of the present invention to provide a field effect transistor which controls an aggregation of silicon atoms incident to heat treatment and has a stable source/drain shape.
In order to achieve the above object, there is provided a field effect transistor according to the present invention, comprising a first semiconductor substrate, a first insulating layer formed over the first semiconductor substrate, a second semiconductor substrate formed over the first insulating layer, an element isolation layer formed in the second semiconductor substrate, and a second insulating layer formed so as to cover each of angular portions on the main surface side of an activation layer defined by the element isolation layer.
Further, there is provided a method of manufacturing a field effect transistor, according to the present invention, which comprises preparing a substrate on which a first semiconductor layer, a first insulating layer and a second semiconductor layer are stacked in order, forming an element isolation layer within the second semiconductor layer, forming a gate electrode over the substrate with a gate insulating film interposed therebetween, forming a second insulating layer so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer, and forming a third semiconductor layer by a selective epitaxial growth method with the gate electrode and the second insulating film as masks.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.